Integrate Circuit With Nanowires

ABSTRACT

The present disclosure provides an integrated circuit (IC). The IC includes a substrate having a metal-oxide-semiconductor (MOS) region. The IC further includes first gate, source and drain regions, having a first length, and second gate, source and drain regions, having a second length. A first nanowire set is disposed in the first gate region, the first nanowire set including a nanowire having a first diameter and connecting to a feature in the first source region and a feature in the first drain region. A second nanowire set is disposed in the second gate region, the second nanowire set including a nanowire having a second diameter and connecting to a feature in the second source region and a feature in the second drain region. The diameters are such that if the first length is greater than the second length, the first diameter is less than the second diameter, and vice versa.

This is a continuation application of U.S. patent application Ser. No. 14/010,196 entitled “Integrated Circuit with Nanowires,” filed Aug. 26, 2013, herein incorporated by reference in its entirety.

BACKGROUND

The integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs.

Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. For example, a three dimensional transistor, such as a semiconductor device with nanowires, has been introduced to replace a planar transistor. It is desired to have improvements in this area.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1A is a diagrammatic perspective view of an integrated circuit (IC) with nanowire according to an embodiment of the present disclosure.

FIG. 1B is a cross-sectional view of an IC with nanowires along line A-A in FIG. 1A.

FIG. 1C is a cross-sectional view of an IC with nanowires along line B-B in FIG. 1A. The line B-B is perpendicular to the line A-A.

FIG. 1D is a diagrammatic perspective view of an IC with nanowire according to an embodiment of the present disclosure.

FIG. 2A is a diagrammatic perspective view of an IC with nanowire according to an embodiment of the present disclosure.

FIGS. 2B-2C and 3A-3B are cross-sectional views of an example IC with nanowire along line A-A in FIG. 2A.

FIG. 4 is a top view of an example IC with nanowire sets.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

The present disclosure is directed to, but not otherwise limited to, a complementary metal-oxide-semiconductor (CMOS) device comprising a P-type metal-oxide-semiconductor (PMOS) device and an N-type metal-oxide-semiconductor (NMOS) device. The following disclosure will continue with a CMOS device example to illustrate various embodiments of the present invention. It is understood, however, that the present disclosure should not be limited to a particular type of device, except as specifically claimed.

FIG. 1A is a side-perspective view of a IC 100 according to an embodiment of the present disclosure. FIGS. 1B and 1C are cross-section views of the IC 100 along line A-A and B-B, respectively, of FIG. 1A. The line B-B is perpendicular to the direction of the line of A-A. FIG. 1D is a side-perspective view of the IC 100 according to another embodiment of the present disclosure. The remaining figures provide side and cross-sectional views of the IC 100, according to various stages of fabrication.

Referring to FIGS. 1A-1C, the IC 100 may be a part of a larger integrated circuit (IC) with a plurality of different devices, regions, and areas, such as a p-type MOS (PMOS) and/or an N-type MOS (NMOS) in and on a substrate 210. As shown in the figure, the substrate 210 includes a source/drain region 212 and a gate region 214 having a length L, which may vary throughout the device. For example, the gate region can have a first length L₁ at one location, and a second length L₂ at another. In the present embodiment, the second length L₂ is larger than 20 nm, which is more than 20% longer than the first length L₁. The gate region 214 having the first length L₁ is referred to as a short channel gate region while the gate region 214 having the second length L₂ is referred to as a long channel gate region. The source/drain regions 212 are separated by the gate region 214.

In the present embodiment, the substrate 210 is a bulk silicon substrate. Alternatively, the substrate 210 may include an elementary semiconductor, such as silicon or germanium in a crystalline structure; a compound semiconductor, such as silicon germanium, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; or combinations thereof. Possible substrates 210 also include a semiconductor-on-insulator substrate, such as silicon-on-insulator (SOI), SiGe-On-Insulator (SGOI), Ge-On-Insulator substrates. For example, SOI substrates are fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and/or other suitable methods.

Some exemplary substrates 210 also include an insulator layer. The insulator layer comprises any suitable material, including silicon oxide, sapphire, and/or combinations thereof. An exemplary insulator layer may be a buried oxide layer (BOX). The insulator is formed by any suitable process, such as implantation (e.g., SIMOX), oxidation, deposition, and/or other suitable process.

The substrate 210 may include various doped regions depending on design requirements as known in the art. The doped regions may be doped with p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; or combinations thereof. The doped regions may be formed directly on the substrate 210, in a P-well structure, in an N-well structure, in a dual-well structure, or using a raised structure.

A recessed first fin 220 is formed in the source/drain region 212. In one embodiment, the recessed first fin 220 is formed by forming a first fin over the substrate 210 first and recessing the first fin. The first fin may be formed by any suitable process including various deposition, photolithography, and/or etching processes. In an example, the first fin is formed by patterning and etching a portion of the silicon substrate 210. In another example, the first fin is formed by patterning and etching a silicon layer deposited overlying an insulator layer (for example, an upper silicon layer of a silicon-insulator-silicon stack of an SOI substrate). It is understood that first fin may include multiple parallel fins formed in a similar manner.

Various isolation regions 230 are formed on the substrate 210 to isolate active regions. For example, the isolation region 230 separates the first fins. The isolation region 230 may be formed using traditional isolation technology, such as shallow trench isolation (STI), to define and electrically isolate the various regions. The isolation region 230 includes silicon oxide, silicon nitride, silicon oxynitride, an air gap, other suitable materials, or combinations thereof. The isolation region 230 is formed by any suitable process. As one example, the formation of an STI includes a photolithography process, etching a trench in the substrate (for example, by using a dry etching and/or wet etching), and filling the trench (for example, by using a chemical vapor deposition process) with one or more dielectric materials. The trenches may be partially filled, as in the present embodiment, where the substrate remaining between trenches forms a fin structure. In some examples, the filled trench may have a multi-layer structure such as a thermal oxide liner layer filled with silicon nitride or silicon oxide.

Then the first fin is recessed to form the recessed first fin 220. The recessing process may include dry etching process, wet etching process, and/or combination thereof. The recessing process may also include a selective wet etch or a selective dry etch. A wet etching solution includes a tetramethylammonium hydroxide (TMAH), a HF/HNO3/CH3COOH solution, or other suitable solution. Dry etching processes include a biased plasma etching process that uses a chlorine-based chemistry. Other dry etchant gasses include CF₄, NF₃, SF₆, and He.

A source/drain feature 240 is formed over the recessed first fin 220 in the source/drain region 212. In one embodiment, a first semiconductor material layer is deposited over the recessed first fin 220 by epitaxial growing processes to form the source/drain feature 240. The epitaxial processes include CVD deposition techniques (e.g., vapor-phase epitaxy (VPE) and/or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and/or other suitable processes. The first semiconductor material layers may include germanium (Ge), silicon (Si), gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), or other suitable materials. The source/drain features 240 may be in-situ doped during the epi process. For example, the epitaxially grown SiGe source/drain features 240 may be doped with boron; and the epitaxially grown Si epi source/drain features 240 may be doped with carbon to form Si:C source/drain features, phosphorous to form Si:P source/drain features, or both carbon and phosphorous to form SiCP source/drain features. In one embodiment, the source/drain features 240 are not in-situ doped, an implantation process (i.e., a junction implant process) is performed to dope the source/drain features 240.

Alternatively, an intra-region 216 is formed between two isolation regions 230, as shown in FIG. 1D. In the intra-region 216, each individual first fin is removed to form a mesa 218 over the substrate 210. A common source/drain feature 240 is formed over the mesa 218 in the source/drain region 212. In one embodiment, the common source/drain feature 240 connects directly to each nanowire set 310 in the gate region 214.

An interlayer dielectric (ILD) layer 250 over the substrate 210, including between the source/drain features 240. The ILD layer 250 includes silicon oxide, oxynitride or other suitable materials. The ILD layer 250 may include a single layer or multiple layers. The ILD layer 250 is formed by a suitable technique, such as CVD, ALD and spin-on (SOG). A chemical mechanical polishing (CMP) process may be performed to planarize the top surface of the ILD layer 250.

In the present embodiments, one or more nanowire sets 310 and high-k/metal gates (HK/MG) 320 are formed over the substrate 210 in the gate region 214. Each nanowire set 310 may have a single nanowire or multiple nanowires. Each nanowire of one nanowire set 310 may connect with respective source/drain feature 240. In one embodiment, the nanowire set 310 connects with the respective source/drain feature 240 directly. The nanowire in the nanowire set 310 may be formed as a rod-shape-like and has a diameter d, which will be described more details later.

The HK/MG 320 may include an interfacial layer (IL) 322, a HK dielectric layer 324 and a MG 326. The IL 322 and HK dielectric layer 324 are disposed over the substrate 210, including conformably wrapping over the nanowire set 310. The HK dielectric layer 324 may include LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfSiO, (Ba,Sr)TiO3 (BST), Al2O3, HfAlO, Si3N4, oxynitrides (SiON), or other suitable materials. The IL 322 and HK dielectric layer 324 may be deposited by ALD or other suitable method.

The MG 326 may include a single layer or multi layers, such as metal layer, liner layer, wetting layer, and adhesion layer. The MG 326 may include Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, or any suitable materials. The MG 326 may be formed by ALD, PVD, CVD, or other suitable process. The MG 326 may be formed separately for the NMOS and PMOS with different metal layers.

The following description will be directed to the formation and structure of the nanowire set 310 in the gate region 214 in process stages, which are earlier than the stage of FIGS. 1A-1C. An example of the formation and structure of the nanowire set 310 is shown in FIGS. 2A-2C.

Referring to FIGS. 2A-2C, a second fin 420 is formed over the substrate 210 in the gate region 214. A formation of the second fin 420 is similar in many respects to the first fin 220 discussed above in association with FIG. 1A. In one embodiment, the recessed first fin 220 and second fin 420 are same fins. The isolation region 230 is disposed between second fins 420.

In the present embodiment, the second fins 420 are recessed and a semiconductor layer stack 430 is formed over the recessed second fin 420. The semiconductor layer stack 430 may include multiple semiconductor layers. Each of these semiconductor layers may have substantial different thickness to each other. The semiconductor layer stack 430 may include germanium (Ge), silicon (Si), gallium arsenide (GaAs), silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), or other suitable materials. The semiconductor layer stack 430 may be deposited by epitaxial growing processes, such as CVD, VPE, UHV-CVD, molecular beam epitaxy, and/or other suitable processes.

In one embodiment, in a PMOS unit (as shown in FIG. 2B), the semiconductor layer stack 430 has (from bottom to top) SiGe (433)/Si(434)/SiGe(433)/Si(434)/SiGe(433)/Si(434) while in NMOS unit (as shown in FIG. 2C) has SiGe (433)/Si (434)/SiGe (433)/Si(434)/SiGe(433).

The semiconductor layer stack 430 may include other suitable combinations of different semiconductor layers. A chemical CMP process may be performed to planarize the top surface of the semiconductor layer stack 430 with the isolation region 230.

In the present embodiment, the isolation region 230 may be etched back to form an open spacing to laterally expose at least a portion of the semiconductor layer stack 430. The etching processes may include selective wet etch or selective dry etch, such that having an adequate etch selectivity with respect to the semiconductor layers stack 430. Various sizes of open spacing are designed to meet certain device structure needs, such as an open spacing for an interconnection contact to be formed later. As an example, a first open spacing s₁ in a first region 610 is substantially larger than a second open spacing s₂ in a second region 620. The second spacing s₂ is substantially larger than a third open spacing s₃ in a second region 630. For Example, in the PMOS unit, s₁ is in a range of 25 nm to 150 nm, s₂ is in a range of 20 nm to 50 nm and s₃ is in a range of 20 nm to 35 nm. For another example, in the NMOS unit, s₁ is in a range of 25 nm to 150 nm, s₂ is in a range of 20 nm to 35 nm and s₃ is in a range of 20 nm to 35 nm.

In the PMOS unit, after the semiconductor layer stack 430 being laterally exposed, a first thermal oxidation process is performed to the exposed semiconductor material layer stack 430 in the gate region 214. During the thermal oxidation process, at least a portion of each semiconductor layers in the semiconductor layer stack 430 is converted to a semiconductor oxide layer. The thermal oxidation process may be conducted in oxygen ambient, or in a combination of steam ambient and oxygen ambient.

In the NMOS unit, after the semiconductor layer stack 430 being laterally exposed, a selective etch process is performed to remove one type semiconductor layer in the semiconductor layer stack 430 and leave another type of semiconductor layer suspend in the gate region 214 (supported by the source/drain feature 240). As an example, SiGe layer 433 is removed by the selective etch and Si layer 434 is suspended in the gate region 214. Then a second thermal oxidation process is performed. The second thermal oxidation process is similar in many respects to the first thermal process discussed above. In one embodiment, the first and second thermal process is one thermal process.

Referring to FIGS. 3A-3B, in the present embodiment, the first/second thermal oxidation is controlled to convert the exposed semiconductor layer stack 430 to a designed configuration of a semiconductor oxide layer stack 530, which has a wire feature 532 in predetermined semiconductor oxide layers. As an example, in the PMOS unit, the SiGe layer 433 is converted to a silicon germanium oxide 533 having a Ge wire feature 532 while the Si layer 434 is fully converted to the silicon oxide layer 534. The Ge wire feature 532 is referred to as Ge nanowire. As another example, in the NMOS unit, the suspended Si layer 434 is converted to the silicon oxide layer 534 having a Si wire feature 535. The Si wire feature 535 is referred to as Si nanowire.

In present embodiment, a diameter of wire feature 532/535 in the first, second and third regions, 610, 620 and 630 are substantially different. In one embodiment, the wire feature 532/535 formed in the first region 610 has a first diameter d₁ which is substantially smaller than a second diameter d₂ of the wire feature 532/535 formed in the second region 620. The second diameter d₂ is substantially smaller than a third diameter d₃ in the third region 630. In one embodiment, the first diameter d₁ is 10% or smaller than the second diameter d₂ The second diameter d₂ is 10% smaller than the third diameter d₃. For example, in the PMOS unit, d₁ is in a range of 4 nm to 15 nm, d₂ is in a range of 1 nm to 3 nm and d₃ is in a range of 1 nm to 3 nm. For another example, in the NMOS unit, d₁ is in a range of 4 nm to 13 nm, d₂ is in a range of 1 nm to 3 nm and d₃ is in a range of 1 nm to 3 nm.

In present embodiment, the diameter of the wire feature 532/535 in the long gate region is substantially smaller than the diameter of the respective wire feature 532/535 in the short gate region. In one embodiment, the diameter of the wire feature 532/535 in the long region is 20% or smaller than the diameter of the respective wire feature 532/535 in the short gate region.

After forming the wire feature 532/535, all layers of the semiconductor oxide stack 530 are removed by a selective etching process and the wire features 532/535 remain in the gate region 214. The wire features 532/535 aligning vertically in a same location of the gate region 214 are referred to as the nanowire set 310, as shown in FIGS. 1A-1C. The HK/MG 320 is formed in the gate region 214, including conformably wrapping over the nanowire set 310, as being described in FIGS. 1A-1C.

Referring to FIG. 4, in one embodiment, a first transistor 710 is adjacent to a second transistor 720, each transistor may include a multiple nanowire sets 310. For the sake of description, diameters of nanowire set 310 located in the very left side, very right side and between them, of the transistor 710, are D₁l, D₁r and D₁c respectively. While diameters of nanowire set 310 located in the very left side, very right side and between them, of the transistor 720, are D₂ 1, D₂r and D₂c respectively. There may be more than one nanowire set 310 located between nanowire sets located in very left and right sides. Spacing between gate electrode 326 of transistor 710 and 720 is Sg. An outer spacing of the transistors 710 are So(l) and So(r) respectively. Spacing within the first transistor 710 is Si. In one embodiment, the first transistor 710 includes three nanowire sets 310. Both of So(l) and So(r) is larger than Si, D_(1c) is larger than D₁l and D₁r. In another embodiment, In one embodiment, the first transistor 710 include four nanowire sets 310. Both of So(l) and So(r) is larger than Si, D_(1c) (there are two nanowire sets between the very left and right nanowire set) are larger than D₁l and D₁r.

The IC 100 may have various additional features and regions for a CMOS or MOS device, known in the art. For example, various contacts/vias/lines and multilayers interconnect features (e.g., metal layers and interlayer dielectrics) are formed over the substrate 210, configured to connect the various features or structures of the IC 100. A multilayer interconnection may include vertical interconnects, such as conventional vias or contacts, and horizontal interconnects, such as metal lines. The various interconnection features may utilize various conductive materials including copper, tungsten, aluminum, and/or silicide, for example, PtSi, CoSi2, NiSi, NiPtSi, WSi2, MoSi2, TaSi2, or other refractory metal silicide. In one example, a damascene and/or dual damascene process is used to form a copper related multilayer interconnection structure.

Based on the above, the present disclosure offers an integrated circuit with nanowire set in a PMOS unit and a NMOS unit. The nanowire set has one or more nanowire. The nanowire is formed with different diameter according to its different environments and locations, such as a size of an open spacing between adjacent nanowire set, or a gate region length.

The present disclosure provides many different embodiments of an integrated circuit (IC). The IC includes a substrate having a metal-oxide-semiconductor (MOS) region, first gate, source and drain regions of a first device in the MOS region. The first gate region has a first length. The IC also includes a first nanowire set disposed in the first gate region, the first nanowire set including a nanowire having a first diameter and connecting to a first feature in the first source region and the first feature in the first drain region. The IC also includes second gate, source and drain regions of a second device in the MOS region. The second gate region has a second length. The IC also includes a second nanowire set disposed in the second gate region, the second nanowire set including a nanowire having a second diameter and connecting to a second feature in the second source region and the second feature in the second drain region. If the first length is greater than the second length, the first diameter is less than the second diameter. If the first length is less than the second length, the first diameter is greater than the second diameter.

In another embodiment, an integrated circuit includes a substrate having a metal-oxide-semiconductor (MOS) region, first gate, source and drain regions of a first device in the MOS region having a first gate region length. The IC also includes a plurality of first nanowire sets disposed in the first gate region having a different spacing between two adjacent first nanowire sets, the first nanowire set including a nanowire having a first diameter and connecting to a common feature in the first source region and a common feature in the first drain region. A diameter of the first nanowire set is different from the first diameter of a different first nanowire set if the different first nanowire set has a different spacing. The IC also includes second gate, source and drain regions of a second device in the MOS region having a second gate region length. The IC also includes a second nanowire set disposed in the second gate region, the second nanowire set including a nanowire having a second diameter and connecting to a feature in the second source region and a feature in the second drain region. If the first length is greater than the second length, the first diameter is less than the second diameter and if the first length is less than the second length, the first diameter is greater than the second diameter.

In yet another embodiment, an integrated circuit (IC) includes a substrate having an N-type metal-oxide-semiconductor (NMOS) region and a P-type metal-oxide-semiconductor (PMOS) region, a plurality of gate structures in the NMOS region and in the PMOS region. A length of the gate structures and a spacing of the gate structures varies between at least two thereof. A nanowire set is disposed in the each of the plurality of gate structures. A diameter of each nanowire in each nanowire set corresponds directly with a relative spacing to an adjacent gate structure, and a relative length of the gate structure.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. 

What is claimed is:
 1. An integrated circuit (IC) comprising: a substrate having a metal-oxide-semiconductor (MOS) region; first gate, source and drain regions of a first device in the MOS region, wherein the first gate region has a first length; a first nanowire set disposed in the first gate region, the first nanowire set including a nanowire having a first diameter and connecting to a first feature in the first source region and a second feature in the first drain region; second gate, source and drain regions of a second device in the MOS region, wherein the second gate region has a second length; and a second nanowire set disposed in the second gate region, the second nanowire set including a nanowire having a second diameter and connecting to a third feature in the second source region and a fourth feature in the second drain region, wherein the first diameter is different from the second diameter.
 2. The IC of claim 1, further comprising: a third nanowire set disposed in the first gate region, wherein the third nanowire set is spaced away from the first nanowire set from a top view and the third nanowire set includes a nanowire having a third diameter and connecting to a fifth feature in the first source region and a sixth feature in the first drain region, wherein the third diameter is different from the first diameter.
 3. The IC of claim 1, further comprising: a third nanowire set disposed in the first gate region, wherein the third nanowire set is spaced away from the first nanowire set from a top view and the third nanowire set includes a nanowire having a third diameter and connecting to the first feature and the second feature.
 4. The IC of claim 3, wherein the third diameter is different from the first diameter.
 5. The IC of claim 1, wherein the first nanowire set includes at least two nanowires aligning vertically in the first gate region and commonly connecting the first feature and the second feature.
 6. The IC of claim 5, wherein the at least two nanowires each are rod-shaped with a diameter equal to the first diameter.
 7. The IC of claim 1, wherein if the first length is greater than the second length, the first diameter is less than the second diameter; and wherein if the first length is less than the second length, the first diameter is greater than the second diameter.
 8. The IC of claim 1, further comprising: at least two nanowire sets disposed in the first gate region adjacent to the first nanowire set, wherein: the at least two nanowire sets and the first nanowire set are spaced away from each other from a top view thereby forming a first plurality of nanowire sets in the first gate region, the first plurality each include a nanowire having a respective diameter, and the respective diameter is smaller when a spacing between adjacent nanowire sets of the first plurality is larger.
 9. The IC of claim 1, wherein the MOS region is an N-type MOS region and nanowires in the first and second nanowire sets contain silicon.
 10. The IC of claim 1, wherein the MOS region is a P-type MOS region and nanowires in the first and second nanowire sets contain germanium.
 11. The IC of claim 1, further comprising an interfacial layer disposed conformably over nanowires in the first and second nanowire sets and a high-k dielectric layer disposed conformably over the interfacial layer.
 12. An integrated circuit (IC) comprising: a substrate having a metal-oxide-semiconductor (MOS) region; a gate region, a source region, and a drain region of a first device in the MOS region; a plurality of nanowire sets disposed in the gate region, wherein: the plurality of nanowire sets are spaced away from each other from a top view, the plurality of nanowire sets each have a respective diameter, and the respective diameter varies when a spacing between adjacent nanowire sets of the plurality varies.
 13. The IC of claim 12, wherein the plurality of nanowire sets include a first nanowire set, a second nanowire set, and at least one nanowire set located between the first and second nanowire sets from a top view, and wherein the at least one nanowire set each have a respective diameter larger than those of the first and second nanowire sets.
 14. The IC of claim 12, further comprising a plurality of first features in the source region and a plurality of second features in the drain region, wherein each of the nanowire sets connects one of the first features and one of the second features respectively.
 15. The IC of claim 12, further comprising a first feature in the source region and a second feature in the drain region, wherein the nanowire sets commonly connect the first feature and the second feature.
 16. The IC of claim 12, wherein the MOS region is an N-type MOS region and nanowires in the nanowire sets contain silicon.
 17. The IC of claim 12, wherein the MOS region is a P-type MOS region and nanowires in the nanowire sets contain germanium.
 18. An integrated circuit (IC) comprising: a substrate; a first source feature and a first drain feature over the substrate; a first nanowire disposed over the substrate, connecting the first source feature and the first drain feature, and having a first diameter and a first length; a second source feature and a second drain feature over the substrate; a second nanowire disposed over the substrate, connecting the second source feature and the second drain feature, and having a second diameter and a second length, wherein the first length is different from the second length and the first diameter is different from the second diameter.
 19. The IC of claim 18, wherein the first length is larger than the second length and the first diameter is smaller than the second diameter.
 20. The IC of claim 18, further comprising a plurality of nanowires disposed over the substrate, aligned with the first nanowire from a top view, commonly connecting the first source feature and the first drain feature, and having the first diameter and the first length. 